There are two major types of random-access memory cells: dynamic and static. Dynamic random-access memories (DRAMs) can be programmed to store a voltage which represents one of two binary values, but require periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods. Static random-access memories are named “static” because they do not require periodic refreshing.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on dies on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.
FIG. 1 illustrates a portion of an exemplary DRAM memory circuit containing two neighboring DRAM cells 42. For each cell, capacitor 44 has two connections, located on opposite sides of the capacitor 44. The first connection is to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to one logical state) of the circuit. The second connection is to the drain of the FET 46. The gate of the FET 46 is connected to the word line 48, and the source of the FET is connected to the bit line 50. This connection enables the word line 48 to control access to the capacitor 44 by allowing or preventing a signal (a logic “0” or a logic “1”) on the bit line 50 to be written to, or read from, the capacitor 44. In some arrangements, the body of the FET 46 is connected to body line 76, which is used to apply a fixed potential to the semiconductor body.
The manufacturing of a DRAM cell typically includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage Vr. As DRAM manufacturing is a highly competitive business, there is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip, especially for densities greater than 256 Megabits. Limitations on cell size reduction include the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of array devices with non-array devices.
Conventional folded bit line cells of the 256 Mbit generation with planar devices have a size of at least 8 F2, where F is the minimum lithographic feature size. If a folded bit line is not used, the cell may be reduced to 6 or 7 F2. To achieve a smaller size, vertical devices could be used. In this manner, cell sizes of 4 F2 may be achieved by using vertical transistors stacked either below or above the cell capacitors, as in the “cross-point cell” of W. F. Richardson et al., A Trench Transistor Cross-Point DRAM Cell, IEDM Technical Digest, pp. 714-17 (1985). Known cross-point cells, which have a memory cell located at the intersection of each bit line and each word line, are expensive and difficult to fabricate because the structure of the array devices is typically incompatible with that of non-array devices. Other known vertical cell DRAMs using stacked capacitors have integration problems due to the extreme topography of the capacitors.
There is needed, therefore, a DRAM cell having an area of less than about 4 F2 that achieves high array density while maintaining structural commonality between array and peripheral (non-array) features. Also needed are simple methods of fabricating a DRAM cell that maximizes common process steps during the formation of array and peripheral devices.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.